The increased complexity of spacecraft and aircraft as well as other vehicles has resulted in a need to incorporate more and more electronic systems in such vehicles. However, the complexity has reached a point where the required and desired electronic systems exceed the available space in the vehicle to accept all such systems. In order to overcome this problem, numerous efforts have and are being made to reduce the size of the electronic packages that make up such electronic systems.
Electronic system evolution has followed the trend of producing more functionality in less volume, at lower weight, and lower cost. Improvements in integrated circuit chip density and functionality have mostly contributed toward improved efficiency, however, advancements in packaging of these devices have also been beneficial. As it becomes more difficult to achieve substantial improvements through integrated circuit technology advances, new packaging approaches have become necessary to obtain density improvements and to allow the full performance potential of interconnected chips to be used. The term "chip" in this description refers to an electrically functional integrated circuit die. The active face of the chip is defined as the surface on which the integrated electronics have been disposed. The back side refers to the surface opposite the active face.
It is known to place an integrated circuit chip in a ceramic or plastic package for protection and then solder the package to a substrate. Typical integrated circuit packages contain only one chip. The package is substantially larger than the chip, thereby limiting the overall packaging density. Conventional packaging systems employing printed circuit boards with single chip packages are unable to provide the required number of chips within a volume and weight which is compatible with the needs of advanced circuit applications.
Applications which require large memory capacity suffer from excessive packaging overhead when single chip packages are used. The present invention relates to integrated circuitry packaging to increase its functional density, through use of a three-dimensional assembly arrangement, and to reduce material and assembly costs.
This invention includes the use of a folded flexible substrate with chips contained on one or both sides of the substrate. The techniques of this invention are applicable for use with any form of commercially available memory chip.
A three dimensional integrated circuit assembly is provided comprising a folded flexible substrate with integrated circuit chips and means for allowing mechanical and electrically functional attachment of integrated circuit chips to one or both sides of the flexible substrate using flip chip assembly techniques. The folded stack of chips and flexible assembly is encapsulated with a polymer molding compound or cast polymer material. The assembly is encapsulated on five sides leaving the pad array side of the stacked chips and flexible circuit assembly uncovered to allow attachment to the next assembly.
In addition, a package substrate is provided upon which the folded substrate is secured with the associated chips. The chips are electrically connected to the flexible substrate and the flexible substrate is in turn electrically connected to the rigid package substrate. A cover is also provided that covers and protects the flexible substrate and the associated chips as well as a portion of the connected rigid package substrate.
This invention provides a method of disposing integrated circuits in a vertical stack which then interfaces with a substrate. The interface area is similar size to that required to ordinarily interface a single integrated circuit chip with a substrate. This invention provides a method for interconnecting two or more chips to a flexible circuit made of a thin, metallized film material. The assembled flexible circuit is folded such that a n-high stack of chips is achieved where n is the number of chips attached to the flexible circuit. Any reasonable number of chips can be assembled in this manner. This creates a three-dimensional arrangement of chips for more effective use of substrate area and allows more chips to be contained in a given volume. Thus, there is provided a ceramic, or other low expansion substrate material, with a means for allowing mechanical and electrically functional attachment of a stack of chips to the substrate using land grid array or ball grid array assembly techniques. A land grid array is formed with an array of conductive bond pads, circular, square or other suitable shape, formed on two opposing substrates. The two opposing patterns are connected together using solder (conductive adhesive or any other suitable conductive material) thus forming an electrical and mechanical connection. A ball grid array is similar except that balls of appropriate size and of a non-melting, but solder wettable (or adhesive bondable material) are included in the pad array so as to increase and control the spacing between the two opposing substrates. The substrate additionally provides an interconnect method for these stacked chips by means of internal vias and circuitry. The circuit packages described herein increase the density (volumetric efficiency) over existing approaches in order to provide higher density, lower weight, and improved functional performance for electronic systems.